FreeScale的MCF5270(不知道是Arm7还是m68k系列的)的C嵌入汇编是怎么写的？
主要想用一个它支持的32x32增强型乘累加指令替代OpenSSL里的一个宏定义，
以提高RSA的运算速度。。。。。
OpenSSL里的一个宏定义：
#define mul_add_c(a,b,c0,c1,c2) \
t=(BN_ULLONG)a*b; \
t1=(BN_ULONG)Lw(t); \
t2=(BN_ULONG)Hw(t); \
c0=(c0+t1)&BN_MASK2; if ((c0) < t1) t2++; \
c1=(c1+t2)&BN_MASK2; if ((c1) < t2) c2++;

汇编指令：
【MAAAC.sz Ry,RxSF,ACCx,ACCw】－－不知道怎么写。。。好像有文章说m68k的嵌入汇编只支持全局变量而不支持局部变量。。。
ColdFire Family Programmer’s Reference Manual, Rev. 3
6-2 Freescale Semiconductor
MAAAC Multiply and Add to First MAAAC
Accumulator, Add to Second Accumulator
First appeared in EMAC_B
Operation: ACCx + (Ry * Rx){<< | >>} SF → ACCx
ACCw + (Ry * Rx){<< | >>} SF → ACCw
Assembler syntax: MAAAC.sz Ry,RxSF,ACCx,ACCw
Attributes: Size = word, longword
Description: Multiply two 16 or 32-bit numbers to produce a 40-bit result, then add this product, shifted
as defined by the scale factor, to an accumulator, ACCx, and also add it to a another accumulator, ACCw.
Instruction Fields:
? Register Rx[6,11–9] field— Specifies a source register operand, where 0x0 is D0,..., 0x7 is D7, 0x8
is A0,..., 0xF is A7. Note that bit 6 of the operation word is the msb of the register number field.
? ACCx field—Specifies the first destination accumulator, ACCx. Bit 4 of the extension word is the
msb and bit 7 of the operation word is the lsb. The value of these two bits specify the accumulator
number as shown in the following table:
Condition
Codes
(MACSR):
N Z V PAVx EV N Set if the msb of the secondary result is set; cleared
otherwise
Z Set if the secondary result is zero; cleared otherwise
V Set if a product or secondary accumulation overflow is
generated or PAVw=1; cleared otherwise
PAVx,wSet if any product or accumulation overflow is
generated; unchanged otherwise
EV Set if secondary accumulation overflows lower 32 bits in
integer mode or lower 40 bits in fractional mode; cleared
otherwise
? ? ? ? ?
Instruction
Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 Register, Rx 0 ACCx
lsb
Rx
msb
0 0 Register, Ry
— — — — sz Scale
Factor
0 U/Lx U/Ly — ACCx
msb
ACCw 0 1
Ext word
[4]
Op word
[7]
Accumulator
0 0 ACC0
0 1 ACC1
1 0 ACC2
1 1 ACC3
Instruction Fields (continued):
? Register Ry[3–0] field — Specifies a source register operand, where 0x0 is D0,..., 0x7 is D7, 0x8
is A0,..., 0xF is A7.
? sz field—Specifies the size of the input operands
— 0 word
— 1 longword
? Scale Factor field —Specifies the scale factor. This field is ignored when using fractional operands.
— 00 none
— 01 product << 1
— 10 reserved
— 11 product >> 1
? U/Lx—Specifies which 16-bit operand of the source register, Rx, is used for a word-sized
operation.
— 0 lower word
— 1 upper word
? U/Ly—Specifies which 16-bit operand of the source register, Ry, is used for a word-sized
operation.
— 0 lower word
— 1 upper word
? ACCw field—Specifies the second destination accumulator, ACCw. 00 = Accumulator 0; 11 =
Accumulator 3.