-- 仿真时间为10000ns
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity testbench is
end testbench;
--------------------------------------------------------------------------------
architecture testbench_arch of testbench is
file RESULTS:text open write_mode is "result.txt"
--编写结果的过程描述
procedure WRITE_RESULTS(CLK :std_logic;
SLEFT :std_logic;
SRIGHT :std_logic;
LOAD :std_logic;
Q :std_logic_vector(3 downto 0)) is
variable L_OUT: line;
begin
write(l_out, now, right, 15, ps);
write(l_out, CLK, right, 2);
write(l_out, SLEFT, right, 2);
write(l_out, SRIGHT, right, 2);
write(l_out, LOAD, right, 2);
write(l_out, STOP, right, 2);
write(l_out, Q, right, 5);
end;

component Johnson_Counter
port(CLK : in std_logic;
LEFT : in std_logic;
LOAD : in std_logic;
Q : in std_logic_vector(3 downto 0);
RIGHT : in std_logic;
STOP : in std_logic);
end component;
signal CLK: std_logic;
signal SLEFT: std_logic;
signal SRIGHT: std_logic;
signal STOP: std_logic;
signal LOAD: std_logic;
signal Q: std_logic_vector(3 downto 0);
signal END_SIM: boolean := false;

begin
UUT: Johnson_Counter;
port map(LEFT => SLEFT,
RIGHT => SRIGHT,
STOP => STOP,
LOAD => LOAD,
CLK => CLK,
Q => Q);
process
begin
LOAD <= '0';
STOP <= '1';
SRIGHT <= '1';
SLEFT <= '1';
wait for 100ns; -- 0000 s
SRIGHT <= '0';
wait for 100ns; -- 0100 ns
LOAD <= '1';
wait for 100ns; -- 0200 ns
LOAD <= '0';
wait for 100ns; -- 0300 ns
SRIGHT <= '1';
wait for 800ns; -- 0400 ns
SLEFT <= '0';
wait for 100ns; -- 1200 ns
SLEFT <= '1';
wait for 1100ns; -- 1300 ns
SRIGHT <= '0';
wait for 100ns; -- 2400 ns
SRIGHT <= '1';
wait for 1100ns; -- 2500 ns
SLEFT <= '0';
wait for 300ns; -- 3600 ns
SLEFT <= '1';
wait for 900ns; -- 3900 ns
STOP <= '0';
wait for 700ns; -- 4800 ns
STOP <= '1';
wait for 400ns; -- 5500 ns
SRIGHT <= '0';
wait for 100ns; -- 5900 ns
LOAD <= '1';
wait for 300ns; -- 0006 us
LOAD <= '0';
SRIGHT <= '1';
wait for 1200ns; -- 6300 ns
STOP <= '0';
wait for 400ns; -- 7500 ns
STOP <= '1';
wait for 400ns; -- 7900 ns
SLEFT <= '0';
wait for 200ns; -- 8300 ns
SLEFT <= '1';
wait for 900ns; -- 8500 ns
SLEFT <= '0';
wait for 200ns; -- 9400 ns
SLEFT <= '1';
wait for 400ns; -- 9600 ns
end_sim <= true;
wait;
end process;
process
begin
if END_SIM = false then
CLK <= '0';
wait for 50ns;
else
wait;
end if;
end process;
WRITE_TO_FILE: WRITE_RESULTS(CLK, SLEFT, SRIGHT, LOAD, STOP, Q);
end testbench_arch;